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Philips Semiconductors
Product specification
Arithmetic Logic Unit
74F381
FEATURES
* Low-input loading minimizes drive requirements * Performs six arithmetic and logic functions * Selectable Low (clear) and High (preset) functions * Carry Generate and Propagate outputs for use with Carry
look-ahead generator
PIN CONFIGURATION
A1 1 B1 2 A0 3 B0 4 S0 5 20 V CC 19 A2 18 B2 17 A3 16 B3 15 Cn 14 P 13 G 12 F3 11 F2
DESCRIPTION
The 74F381 performs three arithmetic and three logic operations on two 4-bit words, A and B. Three additional Select (S0-S2) input codes force the Function outputs Low or High. Carry Propagate (P) and Generate (G) ouputs are provided for use with the 74F182 Carry Look Ahead Generator for high-speed expansion to longer word lengths. For ripple expansion, refer to the 74F382 ALU data sheet. Signals applied to the Select inputs (S0-S2) determine the mode of operation, as indicated in the Function Select Table. An extensive listing of input and output function levels is shown in the Function Table. The circuit performs the arithmetic functions for either active-HIgh or active-Low operands, with output levels in the same convention. In the subtract operating modes, it is necessary to force a Carry (High for active-HIgh operands, Low for active-Low operands) into the Cn input of the least significant package. The Carry Generate (G) and Carry Propagate (P) outputs supply input signals to the 74F182 Carry look-ahead generator for expansion to longer word length, as shown in Figure 1. Note that a 74F382 ALU is used for the most significant package. Typical delays for Figure 1 are given in Table 1.
S1 6 S2 7 F0 8
F1 9 GND 10
SF00921
TYPE 74F381
TYPICAL PROPAGATION DELAY 6.5ns
TYPICAL SUPPLY CURRENT (TOTAL) 59mA
ORDERING INFORMATION
DESCRIPTION 20-pin plastic DIP 20-pin plastic SO COMMERCIAL RANGE VCC = 5V 10%, Tamb = 0C to +70C N74F381N N74F381D
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS A0 - A3 B0 - B3 S0 - S2 Cn P G A operand inputs A operand inputs Function select inputs Carry input Carry Propagate ouptut (active-Low) Carry Generate ouptut (active-Low) DESCRIPTION 74F (U.L.) HIGH/LOW 1.0/4.0 1.0/4.0 1.0/1.0 1.0/4.0 50/33 50/33 50/33 LOAD VALUE HIGH/LOW 20A/2.4mA 20A/2.4mA 20A/0.6mA 20A/2.4mA 1.0mA/20mA 1.0mA/20mA 1.0mA/20mA
F0-F3 Outputs NOTE: One (1.0) FAST unit load is defined as 20A in the High state and 0.6mA in the Low state.
1989 Mar 01
1
853-0418 95907
Philips Semiconductors
Product specification
Arithmetic Logic Unit
74F381
LOGIC SYMBOL
3 4 1 2 19 18 17 16
IEC/IEEE SYMBOL
5 6 7 A0 B0 A1 B1 A2 B2 A3 B3 15 Cn S0 S1 S2 F0 F1 F2 F3 G P 13 14 3 4 1 2 19 4 (1/2) Bl 3 Cl 0 M 0 7 ALU (1/2/3) CP (1/2/3) CG 14 13
15 5 6 7
P Q P Q P Q P Q [1]
8
[2]
9
VCC = Pin 20 GND = Pin 10
8
9
11 12
SF00922
18 17 16
[4]
11
[8]
12
SF00923
1989 Mar 01
2
Philips Semiconductors
Product specification
Arithmetic Logic Unit
74F381
LOGIC DIAGRAM
Cn 15
A0
3
8
F0
B0 A1
4
1
9
F1
B1
2
A2
19
11 F2
B2
18
A3
17
12
F3
14 P B3 16
13 S0 5
G
S1
6
7 S2 VCC = Pin 20 GND = Pin 10
SF00924
1989 Mar 01
3
Philips Semiconductors
Product specification
Arithmetic Logic Unit
74F381
FUNCTION TABLE
INPUTS S0 L H H H H H H H H L L L L L L L L H H H H H H H H L L L L H H H H L L L L H H H H S1 L L L L L L L L L H H H H H H H H H H H H H H H H L L L L L L L L H H H H H H H H S2 L L L L L L L L L L L L L L L L L L L L L L L L L H H H H H H H H H H H H H H H H Cn X L L L L H H H H L L L L H H H H L L L L H H H H X X X X X X X X X X X X X X X X An X L L H H L L H H L L H H L L H H L L H H L L H H L L H H L L H H L L H H L L H H Bn X L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H F0 L H L L H L H H L H L L H L H H L L H H L H L L H L H H L L H H H L L L H H H H H F1 L H H L H L H L L H L H H L L H L L H H H L L L H L H H L L H H H L L L H H H H H OUTPUTS F2 L H H L H L H L L H L H H L L H L L H H H L L L H L H H L L H H H L L L H H H H H F3 L H H L H L H L L H L H H L L H L L H H H L L L H L H H L L H H H L L L H H H H H G L H L H H H L H H H H L H H H L H H H H L H H H L H H H L H H H H L H L H H H H H P L L L H L L L H L L H L L L H L L H L L L H L L L H H L L H H H L L H L L H H H L Preset AB A+B A B A Plus B A minus B B minus A OPERATING MODE Clear
H = High voltage level L = Low voltage level X = Don't care
1989 Mar 01
4
Philips Semiconductors
Product specification
Arithmetic Logic Unit
74F381
FUNCTION SELECT TABLE
SELECT S0 L H L H L H L S1 L L H H L L H S2 L L L L H H H H OPERATING MODE Clear B minus A A minus B A Plus B A AB Preset B A+B
Table 1. 16-Bit Delay Tabulation
PATH SEGMENT Ai or Bi to P Pi to Cn+i (74F182) Cn to F Cn to Cn+4, OVR Total Delay TOWARD F 7.2ns 6.2ns 8.1ns - 21.5ns OUTPUT Cn+4, OVR 7.2ns 6.2ns - 8.0ns 21.4ns
H H H = High voltage level L = Low voltage level
APPLICATION
A0-A3 B0-B3 A4-A7 B4-B7 A8-A11 B8-B11 A12-A15 B12-B15
4 A CIN Cn S F 3 SELECT 3 F0-F3 G0 Cn 74F381 Q B
4 A Cn S P 3 F
4 B
4 A Cn
4 B
4 A Cn
4 B
4
Cn+4 74F382
COUT OVERFLOW
74F381 Q P 3
S F
74F381 Q P 3
S F
OVR
F4-F7 P0 Cn+x G1 P1 Cn+y
F8-F11 G2 P2 Cn+z
F12-F15
74F182
SF00925
Figure 1. 16-bit Look-ahead Carry ALU Expansion
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL VCC VIN IIN VOUT IOUT Tamb TSTG Supply voltage Input voltage Input current Voltage applied to output in High output state Current applied to output in Low output state Operating free-air temperature range Storage temperature range PARAMETER RATING -0.5 to +7.0 -0.5 to +7.0 -30 to +1 -0.5 to VCC 40 0 to +70 -65 to +150 UNIT V V mA V mA
C C
1989 Mar 01
5
Philips Semiconductors
Product specification
Arithmetic Logic Unit
74F381
RECOMMENDED OPERATING CONDITIONS
LIMITS SYMBOL VCC VIH VIL IIK IOH IOL Tamb Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level output current Low-level output current Operating free-air temperature range 0 PARMETER SYMBOL MIN 4.5 2.0 0.8 -18 -1 20 70 NOM 5.0 MAX 5.5 UNIT V V V mA mA mA C
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL PARAMETER TEST CONDITIONS1 VCC = MIN, VIL = MAX, VOH High-level output voltage VIH = MIN, IOH = MAX Low-level output voltage Input clamp voltage Input current at maximum input voltage High-level input current An, Bn, Cn IIL IOS Low-level input current Short-circuit output current3 S0, S1, S2 VCC = MAX, VI = 0.5V VCC = MAX -60 VCC = MIN, VIL = MAX, VIH = MIN, IOL = MAX VCC = MIN, II = IIK VCC = MAX, VI = 7.0V VCC = MAX, VI = 2.7V 10%VCC 5%VCC 10%VCC 5%VCC MIN 2.5 2.7 3.4 0.30 0.30 -0.73 0.50 0.50 -1.2 100 20 -2.4 -0.6 -150 LIMITS TYP2 MAX V V V V V A A mA mA mA UNIT
VOL VIK II IIH
ICC Supply current (total) VCC = MAX 59 89 mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last.
1989 Mar 01
6
Philips Semiconductors
Product specification
Arithmetic Logic Unit
74F381
AC ELECTRICAL CHARACTERISTICS
LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25C VCC = +5.0V CL = 50pF, RL = 500 MIN tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Propagation delay Cn to Fn Propagation delay Any An or Bn to any Fn Propagation delay Sn to Fn Propagation delay An to Bn to G Propagation delay An or Bn to P Propagation delay Sn to G or P Waveform 1 Waveform 1 Waveform 1 Waveform 1 Waveform 1 Waveform 1 2.5 2.5 3.5 3.0 5.0 4.0 3.5 3.0 3.0 3.5 5.0 5.5 TYP 6.0 4.5 7.0 6.0 9.0 7.5 6.5 6.0 5.5 6.0 7.5 8.5 MAX 11.0 6.5 13.0 9.0 20.0 10.5 9.0 8.5 8.0 8.5 11.0 12.5 Tamb = 0C to +70C VCC = +5.0V 10% CL = 50pF, RL = 500 MIN 2.5 2.5 3.5 3.0 5.0 4.0 3.5 3.0 3.0 3.5 5.0 5.0 MAX 12.5 7.5 16.0 10.0 21.5 11.5 10.0 9.0 9.0 9.0 12.5 14.0 ns ns ns ns ns ns UNIT
AC WAVEFORMS
For all waveforms, VM = 1.5V.
VIN
VM tPLH
VM tPHL
VOUT
VM
VM
SF00926
Waveform 1. Propagation Delay for Non-Inverting or Inverting paths
TEST CIRCUIT AND WAVEFORM
VCC NEGATIVE PULSE VIN PULSE GENERATOR RT D.U.T. VOUT 90% VM 10% tTHL (tf ) CL RL tw VM 10% tTLH (tr ) 0V 90% AMP (V)
tTLH (tr ) 90% POSITIVE PULSE VM 10% tw
tTHL (tf ) AMP (V) 90% VM 10% 0V
Test Circuit for Totem-Pole Outputs DEFINITIONS: RL = Load resistor; see AC ELECTRICAL CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC ELECTRICAL CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators.
Input Pulse Definition INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate 1MHz tw 500ns tTLH 2.5ns tTHL 2.5ns
SF00006
1989 Mar 01
7

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